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Lattice Semiconductor
Table 2-2. Interface Signal Descriptions (Continued)
Functional Description
Name
Bits
Active
I/O
Description
Programmable Sampling Rate Mode Only (when Programmable delay = “Yes” )
Sampling Rate. This port is used for feeding the dynamic sampling rate factor of the
rate
rateset
2 to 145
1
—
H
I
I
CIC filter. The width of this port is equal to the next higher integer value of log 2 ( Max
rate +1 ).
Set Sampling Rate. Indicates that input port rate contains a valid rate factor.
Programmable Differential Delay Mode Only (when Programmable rate = “Yes” )
Differential Delay. This port is used for feeding the dynamic differential delay of the
firdf
firdfset
1 or 3
1
—
H
I
I
FIR stages. The width of this port is equal to the next higher integer value of log 2
( Max delay +1 ).
Set Differential Delay. Indicates that input port firdf contains a valid differential
delay factor.
Other Optional Ports
Clock Enable. This signal has the highest priority after rstn . The CIC filter operation
ce
1
H
I
halts as long as ce is held low. Choosing this option will increase resource utilization.
Available only if Clock enable is selected.
System Clear. The optional signal ce , if used, must be held high for clear to be
clear
1
H
I
effective. Choosing this option will increase resource utilization. Available only if
System clear is selected.
Timing Diagrams
Decimator Timing
Interface timing for four cases of decimators are presented in Figure 2-3 and a brief description of each case is
given below. The down-sampling rate is equal to 2 ( Rate = 2) for all cases described.
? Figure 2-3 (a): A new input sample is available at every clock cycle in a continuous manner, so inpvalid signal
is continuously held high. There is one valid output for every Rate clock cycles, as indicated by the outvalid
signal.
? Figure 2-3 (b): A new input sample is available once in every two clock cycles in an intermittent manner. As one
input is given for every two clock cycles, there is one valid output for every four (2* Rate ) clock cycles, as indi-
cated by the outvalid signal.
? Figure 2-3 (c): Interlaced dual-channel input samples x and u are supplied in every clock cycle in a continuous
manner, so ibstart signal is high during the first channel sample x input. For the second channel sample u,
ibstart must be low. Inpvalid is high for each valid input sample. After a few clock cycles of the first input
sample to the IP core, the outvalid signal will be asserted for each valid output data. The signal obstart indi-
cates data for the first channel. Then, subsequent output samples for each channel will be available every
2* Rate clock cycles.
? Figure 2-3 (d): Interlaced dual-channel input samples x and u are supplied in every two-clock clock cycles in an
intermittent manner. After a few clock cycles of the first input sample to the IP core, the outvalid signal will be
asserted for each valid output data. The signal obstart indicates data for the first data. Then, subsequent out-
put samples for each channel will be available every 4* Rate clock cycles.
IPUG42_02.6, August 2010
13
Cascaded Integrator-Comb (CIC) Filter User’s Guide
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